Eliminating I / O Coupling Effects when Interfacing Large - Swing Single - Ended Signals to User I / O Pins on Spartan - 3 Families

The Spartan®-3 families, consisting of Spartan-3, Spartan-3E, and Extended Spartan-3A devices, support an exceptionally robust and flexible I/O feature set, such that the signaling requirements of most applications can easily be met. It is possible to program User I/O pins of these families to handle many different single-ended signal standards. The standard single-ended signaling voltage levels are 1. There are a number of applications for which it is desirable to receive signals with a greater voltage swing than User I/O pins ordinarily permit. The most common use case is receiving 5.0V signals on User I/O pins that are powered for use with one of the standard single-ended signaling levels listed above. In this application note, such signals are referred to as large-swing signals. Large-swing signals might be received by design or might be applied to the User I/O unintentionally from severe positive and/or negative overshoot. The cases of severe positive and/or negative overshoot can occur regardless of the programmed " direction " of a User I/O pin. This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/O in differential pin pairs might occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses the parasitic leakage current behavior. For the specific case of interfacing to the PCI™ bus, see XAPP457, Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI Applications. PCI Bus applications use bidirectional signaling and have unique requirements, which are addressed in XAPP457 and its supporting references. User I/O pins are assigned to signals of the design programmed into the FPGA. These pins are only active when the FPGA operates in user mode. Before then, during configuration, they are either in a high impedance state or weakly pulled up. User I/O pins are organized in banks around the perimeter of the die. Each Spartan-3 device has eight banks, while Spartan-3E and Extended Spartan-3A (Spartan-3A, Spartan-3AN, and Spartan-3A DSP) devices have four banks. An independent V CCO rail per bank (for example, VCCO_0, VCCO_1, etc.) powers the output buffers associated with the User I/O pins in each bank. User I/O input buffers are powered by V CCO , V CCINT , or V CCAUX , depending on the device family and the signal standard in use. Dual-purpose pins function as specific configuration-related …